Negative edge triggered flip flop timing diagram generator#

Negative edge triggered flip flop timing diagram generator#

The proposed dual-mode pulse generator is shown in Figure 1(a). The proposed design also exhibits competitive power and speed performance when compared with other single-mode P-FF design. The circuit overhead of dual-mode operations is minimized by successfully integrating both pulse generation logics into a unified module. Herein, in this paper, we will present a novel dual-mode pulse-triggered FF design, with emphasis on low circuit complexity. FFs used in FPGAs or structured ASIC are another example where the selection of triggering mode is required. A dual-mode FF can perfectly serve the purpose without employing two FFs working on different clock frequencies. For example, in many communication baseband circuits, data oversampling is required in the initial synchronization acquiring phase, while the clock rate is reduced to a normal frequency later on for power saving. An FF with dual triggering modes is useful in many applications. None of them can provide both triggering modes in one design. Various explicit type P-FFs supporting either single- or double-edge-triggered operations have been proposed. In this paper, we will therefore focus on the explicit type designs only. This gives the explicit type designs advantages in both circuit complexity and power consumption. In design practices, one pulse generation circuitry can be shared among FFs within the same register in explicit pulse generation. Although implicit pulse generation is often considered as more power efficient, the lengthened signal discharge path in latch design leads to inferior timing characteristics. In explicit type P-FF, the designs of pulse generator and the latch are separate. In implicit type P-FF, the pulse generator is a built-in logic of the latch design, and no explicit pulse signals are generated. Pulse-triggered FFs (P-FFs) can be classified into two types, that is, implicit and explicit, depending on the implementation of pulse generator. Another advantage of pulse-triggered FFs is that they allow time borrowing across cycle boundaries and feature zero or even negative setup time. It can thus provide higher toggle rate than the conventional FF can and is found useful in high speed applications. The circuit complexity of a pulse-triggered FF is thus greatly simplified since only one latch, as opposed to two latches in master-slave configuration, is needed. Since the pulses are generated on the transition edges of the clock signal and very narrow in pulse width, the latch acts like an edge-triggered FF. A pulse-triggered FF consists of a pulse generator (also called transition detector) for strobe signals and a latch for data storage. To reduce the circuit complexity, pulse-triggered FFs have been considered as a popular alternative to the conventional master-slave-based FF these days. FFs thus contribute a significant portion of gate count to the overall system design. In particular, digital designs nowadays often adopt intensive pipelining techniques and employ many FF-rich modules such as register file and shift register. IntroductionР”Р‡lip-flops (FFs) are the basic storage elements used extensively in all kinds of digital designs. Postlayout simulations in TSMC 1P6M 0.18 РћСm CMOS process model also indicate that the proposed design is as efficient as its single-mode counterpart in various performance metrics. Due to the novelty in pulse generator design, the layout area overhead is only 8% when compared with other single-mode counterpart design. It supports both single-edge- and double-edge-triggered operations subject to a mode select control. A low complexity dual-mode pulse-triggered FF design for wireless baseband processing is presented in this paper.